1. Field of the Invention
The present invention relates to a logic circuit which is equipped with a shift function and a count function.
2. Description of the Prior Art
When inputting an initial value into a counter and then taking out the counted result after a predetermined number of count operating, the use of a small scale integrated circuit (SSI) or the like, in which the bits of data handled are input in parallel as the initial value to the counter and output in parallel as the counted value, does not pose any particular problems. In a large scale integrated circuit (LSI), however, such parallel input of the initial value into the counter from the outside and parallel output of the count value are difficult because of an increase in the number of bits of data handled and a limitation on the number of pins that can be used. Therefore, it is general practice in the prior art to supply the initial value data in serial form from the outside, convert the serial data, by a serial-parallel converting register, to parallel form for input to the counter and convert the count value of the counter in parallel form, by a parallel-serial converting register, to serial form for output.
FIG. 1 illustrates the arrangement of a conventional 4-bit counter/shift register employing a shift register and a counter. In FIG. 1, on the left-hand side of the broken line is a shift register part and on the right-hand side is a counter part. Reference numerals 1-1, 1-2, 1-3 and 1-4 indicate circuits for loading data in parallel; 2-1, 2-2, 2-3 and 2-4 designate cascade-connected flip-flops (FF), each of which is usually a delay (D) flip-flop or delay (D) latch; 3-1, 3-2, 3-3 and 3-4 identify gate circuits for loading data into the counter part and causing it to perform the count operation; 4-1, 4-2, 4-3 and 4-4 denote cascade-connected flip-flops (FF), each of which is usually a J-K flip-flop; and 5 indicates a carry output circuit.
The circuit of FIG. 1 perfroms in following manner. First, the initial value of each bit of the counter is entered in the shift register part. This is achieved by raising the level of a signal on a SHIFT LOAD terminal to a high level "H" in order to enter the initial value of the counter into the bit of each of the shift registers from a SERIAL DATA IN terminal. Needless to say, it is also possible, in this circuit, to set each bit of the counter to a low level "L" by a signal on a 7 COUNT terminal. Next, by raising the level of a signal at a COUNT LOAD terminal to the high level "H", the initial value is loaded into the counter part from the shift register part.
The counting operation is carried out in the following manner. First, the level of the signal at a COUNT LOAD terminal is lowered to the low level "L" and, at this time, a carry signal is applied to a CARRY IN terminal. When the signal at the CARRY IN terminal is at the high level, a carry exists and when the level of this signal is low, no carry exists.
Upon completion of the counting operation, the count result is loaded into the shift register part. This is performed by lowering the level of the signal at the SHIFT LOAD terminal to the low level L. Thereafter, data of each bit in the shift register part is outputted from a SERIAL OUT terminal.
FIG. 2 is a circuit diagram showing a specific example of the circuit arrangement of the counter/register depicted in FIG. 1. In FIG. 2, parts corresponding to those in FIG. 1 are identified by the same reference numerals and characters. The load circuits 1-1 to 1-4 are each constructed with three gates, and accordingly twelve gates are needed. The delay flip-flops 2-1 to 2-4 are each constructed with six gates; hence, 24 gates are required. The gates 3-1 to 3-4 are constructed with 19 gates in all. The J-K flip-flops 4-1 to 4-4 are each constructed with eight gates, and consequently 32 gates are required. Therefore, the counter/shift register of FIG. 1, except the carry output circuit and so forth, requires a total of about 87 gates.
As described above, the prior art circuit employs a register with the same number of bits as the counter for the serial-input, count and serial-output operations. Accordingly, for n-bit counting, the entire circuit arrangement including the register requires 2n flip-flops, along with a large number of gates. It is wasteful to include, for each bit, two flip-flops, one for register use and the other for counter use, and since the register and the counter do not overlap in their operational timing, it is possible to perform the both functions with one flip-flop per bit.